module IFID(
    input clk, rst, IFIDFlush,       // IFIDFlush clear signals
    input IFIDWait,                  // IFIDWait keep signals
    input JRFlush_from_ID,
    input JFlush_from_ID,
    input JALFlush_from_WB,
    input PCScr,
    input [31:0] inst_from_IF,       // current instruction
    input [31:0] pc4_form_IF,        // next pc value
    output reg [31:0] pc4_to_ID, inst_to_ID
);

//wire IFIDWait_temp, JRFlush_temp, Jflush_temp, Jalflush_temp, Pcscr_temp;
//wire [31:0] inst_temp1, pc4_temp1,inst_temp2, pc4_temp2;

//assign inst_temp1 = (IFIDFlush|JRFlush_from_ID|JALFlush_from_WB|JFlush_from_ID|PCScr)?  32'b0:inst_from_IF;
//assign pc4_temp1 = (IFIDFlush|JRFlush_from_ID|JALFlush_from_WB|JFlush_from_ID|PCScr)?  32'b0:pc4_form_IF;

//assign inst_temp2 = (IFIDWait)?  inst_to_ID:inst_temp1;
//assign pc4_temp2 = (IFIDWait)?  pc4_to_ID:pc4_temp1;

always@(posedge clk or negedge rst)begin
    if(!rst)
    begin
        pc4_to_ID <= 32'b0;
        inst_to_ID <= 32'b0;
    end 
    else if(IFIDFlush|JRFlush_from_ID|JALFlush_from_WB|JFlush_from_ID|PCScr)begin
        pc4_to_ID <= 32'b0;
        inst_to_ID <= 32'b0;
    end
    else if(!IFIDWait) begin
         pc4_to_ID <= pc4_form_IF;
        inst_to_ID <= inst_from_IF;
   end
    else begin       
        pc4_to_ID <= pc4_to_ID;
        inst_to_ID <= inst_to_ID;
    end
end
endmodule